1. Field of the Invention
The present invention relates to a static random access memory (SRAM), and more particularly, to a SRAM with a shared contact for a small dimension semiconductor device.
2. Description of the Prior Art
Recently, demand for semiconductor devices has rapidly increased owing to widespread use of integrated electronic circuit. In particularly, static random access memory (SRAM) has become a basic and elementary component used in integrated circuits (ICs), such as semiconductor memory devices. More particularly, as more than hundreds or thousands of electrical components are integrated into the ICs, a means for scaling down the dimension of the SRAM and reducing fabrication cost has become imperative.
FIGS. 1A to 1F show cross-sectional views of a traditional static random access memory (SRAM), where the cross section shown in FIG. 1B has additional silicon oxide 250 and photo resist layer 270. An N-type semiconductor device, for example, has a source region 260A and a drain region 260B doped with N-type ions, and which usually designated as N.sup.+ regions. The substrate 100 usually has a P-type well, the gate 140 is composed of polysilicon , and the spacers 240. The cross section shown in FIG. 1C has the etched photo resist layer 270 and local spacer. Because the etched spacers result in the destruction of the lightly doped drain regions, the process of semiconductor devices was affected. The cross section shown in FIG. 1D has the formed source/drain regions 260A and 260B and has the etched local dielectrics 250. The cross section shown in FIG. 1E has additional silicidation regions 280A1, 280A2, 280B and 280C. Furthermore, the process of scaling down SRAM should also be correspondingly simplified. For the foregoing reasons, there is a need for a SRAM with small dimension and more simplification fabrication.